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  • Research Article
  • Open Access

DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

  • 1Email author,
  • 1 and
  • 2
EURASIP Journal on Embedded Systems20072008:562326

https://doi.org/10.1155/2008/562326

  • Received: 4 June 2007
  • Accepted: 15 October 2007
  • Published:

Abstract

Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13  m CMOS SoC implementing a specialized DART cluster is presented.

Keywords

  • Energy Efficiency
  • Mobile Communication
  • Interconnection Network
  • High Energy Efficiency
  • VLSI Design

Publisher note

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Authors’ Affiliations

(1)
IRISA/R2D2, 6 Rue de Kerampont, Lannion, 22300, France
(2)
CEA, LIST, Embedded Computing Laboratory, Mailbox 94, Gif-sur-Yvette, F-91191, France

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