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  • Research Article
  • Open Access

Model-Driven Validation of SystemC Designs

EURASIP Journal on Embedded Systems20082008:519474

  • Received: 1 October 2007
  • Accepted: 7 April 2008
  • Published:


Functional test generation for dynamic validation of current system level designs is a challenging task. Manual test writing or automated random test generation techniques are often used for such validation practices. However, directing tests to particular reachable states of a SystemC model is often difficult, especially when these models are large and complex. In this work, we present a model-driven methodology for generating directed tests that take the SystemC model under validation to specific reachable states. This allows the validation to uncover very specific scenarios which lead to different corner cases. Our formal modeling is done entirely within the Microsoft SpecExplorer tool to formally describe the specification of the system under validation in the formal notation of AsmL. We also exploit SpecExplorer's abilities for state space exploration for our test generation, and its APIs for connecting the model to real programs to drive the validation of SystemC models with the generated test cases.


  • Test Generation
  • Random Test
  • Reachable State
  • Manual Test
  • Publisher Note

Publisher note

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Authors’ Affiliations

Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 545K Cory Hall, Berkeley, CA 94720, USA
Formal Engineering Research with Models, Abstractions and Transformations, Virginia Tech., 302 Whittemore Hall, Blacksburg, VA 24060, USA


© H. D. Patel and S. K. Shukla. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.