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Open Access

Flexible Hardware-Based Stereo Matching

  • Kristian Ambrosch1Email author,
  • Wilfried Kubinger1,
  • Martin Humenberger1 and
  • Andreas Steininger2
EURASIP Journal on Embedded Systems20092008:386059

Received: 28 February 2008

Accepted: 20 November 2008

Published: 18 January 2009


To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC) as well as field programmable gate array (FPGA) implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs), rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.


Block SizeField Programmable Gate ArrayResource UsageElectronic CircuitFull Article

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Authors’ Affiliations

Austrian Research Centers GmbH-ARC, Vienna, Austria
Institute of Computer Engineering, Vienna University of Technology, Vienna, Austria


© Kristian Ambrosch et al. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.