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Flexible Hardware-Based Stereo Matching
EURASIP Journal on Embedded Systems volume 2008, Article number: 386059 (2009)
To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC) as well as field programmable gate array (FPGA) implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs), rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.
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Ambrosch, K., Kubinger, W., Humenberger, M. et al. Flexible Hardware-Based Stereo Matching. J Embedded Systems 2008, 386059 (2009). https://doi.org/10.1155/2008/386059
- Block Size
- Field Programmable Gate Array
- Resource Usage
- Electronic Circuit
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