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  • Research Article
  • Open Access

Flexible Hardware-Based Stereo Matching

  • 1Email author,
  • 1,
  • 1 and
  • 2
EURASIP Journal on Embedded Systems20092008:386059

https://doi.org/10.1155/2008/386059

  • Received: 28 February 2008
  • Accepted: 20 November 2008
  • Published:

Abstract

To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC) as well as field programmable gate array (FPGA) implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs), rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.

Keywords

  • Block Size
  • Field Programmable Gate Array
  • Resource Usage
  • Electronic Circuit
  • Full Article

Publisher note

To access the full article, please see PDF.

Authors’ Affiliations

(1)
Austrian Research Centers GmbH-ARC, 1220 Vienna, Austria
(2)
Institute of Computer Engineering, Vienna University of Technology, 1040 Vienna, Austria

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