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EURASIP Journal on Embedded Systems
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Flexible Hardware-Based Stereo Matching

EURASIP Journal on Embedded Systems volume 2008, Article number: 386059 (2009) Cite this article

Abstract

To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC) as well as field programmable gate array (FPGA) implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs), rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.

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Authors and Affiliations

  1. Austrian Research Centers GmbH-ARC, 1220, Vienna, Austria

    Karina Ambrosch, Wilfried Kubinger & Martin Humenberger

  2. Institute of Computer Engineering, Vienna University of Technology, 1040, Vienna, Austria

    Andreas Steininger

Authors
  1. Karina Ambrosch
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  2. Wilfried Kubinger
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  3. Martin Humenberger
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  4. Andreas Steininger
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Corresponding author

Correspondence to Karina Ambrosch.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Ambrosch, K., Kubinger, W., Humenberger, M. et al. Flexible Hardware-Based Stereo Matching. J Embedded Systems 2008, 386059 (2009). https://doi.org/10.1155/2008/386059

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  • DOI: https://doi.org/10.1155/2008/386059

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