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  • Research Article
  • Open Access

SoC Design Approach Using Convertibility Verification

EURASIP Journal on Embedded Systems20082008:296206

  • Received: 13 April 2008
  • Accepted: 23 October 2008
  • Published:


Compositional design of systems on chip from preverified components helps to achieve shorter design cycles and time to market. However, the design process is affected by the issue of protocol mismatches, where two components fail to communicate with each other due to protocol differences. Convertibility verification, which involves the automatic generation of a converter to facilitate communication between two mismatched components, is a collection of techniques to address protocol mismatches. We present an approach to convertibility verification using module checking. We use Kripke structures to represent protocols and the temporal logic to describe desired system behavior. A tableau-based converter generation algorithm is presented which is shown to be sound and complete. We have developed a prototype implementation of the proposed algorithm and have used it to verify that it can handle many classical protocol mismatch problems along with SoC problems. The initial idea for -based convertibility verification was presented at SLA++P '07 as presented in the work by Roopak Sinha et al. 2008.


  • Control Structure
  • Design Approach
  • Electronic Circuit
  • Full Article
  • Publisher Note

Publisher note

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Authors’ Affiliations

Department of Electrical and Computer Engineering, The University of Auckland, Auckland, 1142, New Zealand
Department of Computer Science, Iowa State University, Ames, Iowa 50011, USA


© Roopak Sinha et al. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.