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  • Research Article
  • Open Access

Using Visual Specifications in Verification of Industrial Automation Controllers

EURASIP Journal on Embedded Systems20072008:251957

https://doi.org/10.1155/2008/251957

  • Received: 3 February 2007
  • Accepted: 4 November 2007
  • Published:

Abstract

This paper deals with further development of a graphical specification language resembling timing-diagrams and allowing specification of partially ordered events in input and output signals. The language specifically aims at application in modular modelling of industrial automation systems and their formal verification via model-checking. The graphical specifications are translated into a model which is connected with the original model under study.

Keywords

  • Output Signal
  • Original Model
  • Control Structure
  • Automation System
  • Electronic Circuit

Publisher note

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Authors’ Affiliations

(1)
Department of Electrical and Computer Engineering, University of Auckland, Auckland, 1142, New Zealand
(2)
Controle Soluções em Mecatrônica Ltda., Rua Mauro Nerbass, 72, Lages, SC CEP 88024-420, Brazil

Copyright

© V. Vyatkin and G. Bouzon. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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