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Using Visual Specifications in Verification of Industrial Automation Controllers
EURASIP Journal on Embedded Systems volume 2008, Article number: 251957 (2007)
This paper deals with further development of a graphical specification language resembling timing-diagrams and allowing specification of partially ordered events in input and output signals. The language specifically aims at application in modular modelling of industrial automation systems and their formal verification via model-checking. The graphical specifications are translated into a model which is connected with the original model under study.
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Vyatkin, V., Bouzon, G. Using Visual Specifications in Verification of Industrial Automation Controllers. J Embedded Systems 2008, 251957 (2007). https://doi.org/10.1155/2008/251957
- Output Signal
- Original Model
- Control Structure
- Automation System
- Electronic Circuit