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EURASIP Journal on Embedded Systems
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Using Visual Specifications in Verification of Industrial Automation Controllers

EURASIP Journal on Embedded Systems volume 2008, Article number: 251957 (2007) Cite this article

Abstract

This paper deals with further development of a graphical specification language resembling timing-diagrams and allowing specification of partially ordered events in input and output signals. The language specifically aims at application in modular modelling of industrial automation systems and their formal verification via model-checking. The graphical specifications are translated into a model which is connected with the original model under study.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Auckland, Auckland, 1142, New Zealand

    Valeriy Vyatkin

  2. Controle Soluções em Mecatrônica Ltda., Rua Mauro Nerbass, 72, Lages, SC CEP 88024-420, Brazil

    Gustavo Bouzon

Authors
  1. Valeriy Vyatkin
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  2. Gustavo Bouzon
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Correspondence to Valeriy Vyatkin.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Vyatkin, V., Bouzon, G. Using Visual Specifications in Verification of Industrial Automation Controllers. J Embedded Systems 2008, 251957 (2007). https://doi.org/10.1155/2008/251957

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  • DOI: https://doi.org/10.1155/2008/251957

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