Open Access

Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

EURASIP Journal on Embedded Systems20072008:231940

https://doi.org/10.1155/2008/231940

Received: 24 May 2007

Accepted: 15 October 2007

Published: 23 October 2007

Abstract

We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.

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Authors’ Affiliations

(1)
Department of Computer Science and Information Engineering, National Chung Cheng University

Copyright

© C.-H. Huang and P.-A. Hsiung. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.