Editorial to special issue on energy efficient architectures for embedded systems
© The Author(s) 2016
Received: 24 August 2016
Accepted: 24 August 2016
Published: 18 October 2016
In the last decades, a significant boost in embedded computing systems performance has been observed in several different domains, mostly due to technology scaling and to the ever increasing exploitation of parallel processing architectures .
However, although conventional approaches relying on homogeneous/heterogeneous chip-multiprocessor aggregates already allow achieving a significant performance level , important compromises are necessary in order to cope with the strict energy efficiency requirements present in many embedded application domains (e.g. mobile, battery supplied and hand-held devices) .
As a consequence, energy efficiency is gradually becoming one fundamental constraint and requisite for embedded systems design, often requiring the adoption of new technologies [4, 5] and micro-architecture design approaches [6–10].
This special issue (SI) of the EURASIP Journal on Embedded Systems (Springer) entitled “Energy Efficient Architectures for Embedded Systems” is mainly focused on new design and development trends of energy efficient processing architectures for embedded systems. The collection of papers presented here emphasizes several aspects of this research domain, including not only architectures and specific design methods but also more technological aspects related to micro-architecture design, memory hierarchies, communication mechanisms and tools/algorithms for energy/power management and control.
The call for papers resulted in nine manuscript submissions. For each submission, at least two reviewers examined its quality, together with the guest editors and the editor-in-chief. Finally, four papers were selected for publication that cover the following three prominent topics in embedded system design: computer microarchitectures for energy efficiency, energy/power models and management strategies, and energy-efficient memory hierarchy subsystems.
The paper entitled “A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection”, by Muiris Woulfe and Michael Manzke, presents a hybrid processing system spanning a fixed-function microarchitecture and a general-purpose microprocessor, designed to increase the throughput and reduce the power dissipation of collision detection relative to what can be achieved using CPUs or GPUs alone. The primary component is one of two novel microarchitectures designed to perform the principal elements of broad-phase collision detection. Both microarchitectures consist of processing pipelines comprising a plurality of memories, which rearrange the input into a format that maximizes parallelism and bandwidth. The two microarchitectures are combined with the remainder of the system through an original method for sharing data between a ray tracer and the collision-detection microarchitectures to minimize data structure construction costs. According to the presented experimental evaluation using several benchmarks of varying object counts (for over one million objects), the proposed design attains an acceleration of 812x relative to a CPU and an acceleration of 161x relative to a GPU. Furthermore, it is also characterized by being energy efficient, which enables the mitigation of silicon power-density challenges, while making the design amenable to both mobile and wearable computing devices.
The paper on “Dynamic Power Management for Reactive Stream Processing on the SCC Tiled Architecture”, by Nilesh Karavadara, Michael Zolda, Vu Thien Nga Nguyen, Jens Knoop, and Raimund Kirner, presents an execution framework for reactive stream processing systems (RSPS) that provides a dynamic voltage and frequency scaling (DVFS) strategy to optimize the power consumption. The devised DVFS strategy is able to cope with a variable system load, by adjusting the frequency and voltage (in runtime) to the required computational resources, based on the observation of the input and output rates of the RSPS, as well as on the number of workers waiting for new work, to predict overload and underload situations. In contrast to many other approaches, the devised mechanism does not require the ability to control the power setting of individual computational units, making it suitable for tiled many-core processors like the Intel single-chip cloud computer (SCC). According to the presented experimental validation run on SCC, the proposed DVFS strategy for RSPS can significantly reduce the resulting energy consumption.
The paper entitled “Sensing User Context and Habits for Run-Time Energy Optimization”, by Ismat Chaib Draa, Smail Niar, Jamel Tayeb, Emmanuelle Grislin, and Mikael Desertot, is focused on optimizing the energy consumption in mobile handheld devices, by observing that the number of active sensors and communication tools impact the energy consumption, battery life and system reliability. Firstly, it presents a tool to analyze the user/application interaction and to understand how the different hardware components are used at run time. Then, it makes use of machine learning methods to identify and classify user behaviors and habits information. By using this tool, a software layer has been developed to control and optimize (at run-time) the system component activities that have the highest impact on the energy consumption. The tool also allows predicting future application usages. With this approach, screen brightness, CPU frequency, Wi-Fi connectivity and playback sound-level can be optimized while meeting the applications and the user requirements. According to the presented experimental evaluation, the proposed solution can lower the energy consumption by up to 30 % vs. the out-of-the-box power governor, while maintaining a negligible system overhead.
The paper on “Energy-Aware Memory Management for Embedded Multidimensional Signal Processing Applications”, by Florin Balasa, Noha Abuaesh, Cristian V. Gingu, Ilie I. Luican, and Hongwei Zhu, presents an electronic design automation (EDA) methodology for the high-level design of hierarchical memory architectures in embedded data-intensive applications, mainly in the area of multidimensional signal processing. Contrasting to previous works, the problems of data assignment to the memory layers, mapping of signals into the physical memories, and banking the on-chip memory are addressed in a consistent way using a single formal model. To accomplish such objective, the devised memory management framework makes use of techniques specific to the integral polyhedra-based dependence analysis. When compared to earlier approaches, the added flexibility of this assignment model led to reductions in both the static and dynamic energy consumption in the hierarchical memory subsystem.
To conclude, the guest editors would like to thank all the authors and the reviewers for their contribution and support for this special issue. We are confident that the presented set of research papers constitute relevant steps towards pursuing the challenging task of coping with the strict energy efficiency requirements that are imposed on embedded system application domains.
Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License(http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
- N Neves, H Mendes, RJ Chaves, P Tomás, N Roma, Morphable hundred-core heterogeneous architecture for energy-aware computation. IET Comput. Digit. Tech. 9(1), 49–62 (2015).View ArticleGoogle Scholar
- E Blem, J Menon, K Sankaralingam, in IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’2013). Power struggles: revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures (IEEE Computer SocietyWashington, DC, 2013), pp. 1–12.Google Scholar
- J Gubbi, R Buyya, S Marusic, M Palaniswami, Internet of things (IoT): a vision, architectural elements, and future directions. Future Generation Comput. Syst. 29(7), 1645–1660 (2013).View ArticleGoogle Scholar
- JL Nunez-Yanez, M Hosseinabady, A Beldachi, Energy optimization in commercial FPGAs with voltage, frequency and logic scaling. IEEE Trans. Comput. 65(5), 1484–1493 (2016).MathSciNetView ArticleGoogle Scholar
- MT Chang, P Rosenfeld, SL Lu, B Jacob, in IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’2013). Technology comparison for large last-level caches (L 3 C s): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM (IEEE Computer SocietyWashington, DC, 2013), pp. 143–154.Google Scholar
- J Yun, DK Singh, DY Suh, Dynamic voltage and frequency scaling over delay-constrained mobile multimedia service using approximated relative complexity estimation. EURASIP J. Embedded Syst. 2013(1), 1–13 (2013).View ArticleGoogle Scholar
- V Hanumaiah, S Vrudhula, Energy-efficient operation of multicore processors by DVFS, task migration, and active cooling. IEEE Trans. Comput. 63(2), 349–360 (2014).MathSciNetView ArticleGoogle Scholar
- S Mittal, A survey of architectural techniques for improving cache power efficiency. Sustain. Comput. Inf. Syst. 4(1), 33–43 (2014).Google Scholar
- H Esmaeilzadeh, A Sampson, L Ceze, D Burger, in Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVII. Architecture support for disciplined approximate programming (ACMNew York, 2012), pp. 301–312.Google Scholar
- JW Choi, D Bedard, R Fowler, R Vuduc, in IEEE 27th International Symposium on Parallel Distributed Processing (IPDPS’2013). A roofline model of energy (IEEE Computer SocietyWashington, DC, 2013), pp. 661–672.View ArticleGoogle Scholar