Open Access

Formal Methods for Scheduling of Latency-Insensitive Designs

EURASIP Journal on Embedded Systems20072007:039161

DOI: 10.1155/2007/39161

Received: 1 July 2006

Accepted: 11 May 2007

Published: 30 August 2007

Abstract

Latency-insensitive design (LID) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behavior is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: relay-stations (RS) and shell-wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can be then formally verified. As turns out, resulting behavior is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs throughput equalization, adding integer latencies wherever possible; residual cases require introduction of fractional registers (FRs) at specific locations. Benchmark results are presented, run on our Kpassa tool implementation.

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Authors’ Affiliations

(1)
Aoste project-team, INRIA Sophia-Antipolis, 2004 rouye des Iucioles

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Copyright

© Julien Boucaron et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.