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Table 10 Difference of simulation and proposed model under multi-programed workloads for a 16-core CMP

From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age

Workload CMP Cores (%) Cache hierarchy (%) NoC (%)
MB1 Baseline 0.084 6.871 20.929
Hybrid 4.545 11.111 16.667
MB2 Baseline 3.357 5.852 16.847
Hybrid 5.149 13.725 12.903
MD1 Baseline 3.774 4.755 2.069
Hybrid 2.449 9.222 4.643
MD2 Baseline 3.846 5.797 3.226
Hybrid 5.263 7.018 6.452
CB1 Baseline 3.333 3.279 6.250
Hybrid 1.754 8.333 3.448
CB2 Baseline 3.226 6.154 3.030
Hybrid 1.695 6.000 − 3.125
Mix1 Baseline 3.509 2.941 6.667
Hybrid 1.852 5.769 − 3.226
Mix2 Baseline 3.448 2.899 6.452
Hybrid 9.091 1.754 3.333
Average Baseline 3.072 4.819 8.184
Hybrid 3.975 7.867 5.137