Fig. 7
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age

Validation of the power model under multi-threaded workloads for a 16-core CMP and b 64-core CMP
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
Validation of the power model under multi-threaded workloads for a 16-core CMP and b 64-core CMP