Fig. 6
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
An example of a multi-threaded application with D parallel threads
Fig. 6 | EURASIP Journal on Embedded Systems
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
An example of a multi-threaded application with D parallel threads
