Fig. 6
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
An example of a multi-threaded application with D parallel threads
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Fig. 6 | EURASIP Journal on Embedded Systems
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From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
An example of a multi-threaded application with D parallel threads
