Fig. 5
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age

The style of using cache hierarchy in a a multi-programed workload and b a multithreaded workload
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
The style of using cache hierarchy in a a multi-programed workload and b a multithreaded workload