Fig. 33
Iteration time per cycle for BRAM-based HW_v2. a Full simulation. b Longest iteration. c Most common iteration time. d Shortest iteration time (stage 3 not required)
Fig. 33 | EURASIP Journal on Embedded Systems
Iteration time per cycle for BRAM-based HW_v2. a Full simulation. b Longest iteration. c Most common iteration time. d Shortest iteration time (stage 3 not required)