Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

EURASIP Journal on Embedded Systems

Table 4 Performance Comparison: SRH and DRH vs. Software on MicroBlaze

	Execution time in AXI_clk_cycles			Speedup
	SRH	DRH	Sw on MicroBlaze	SRH vs. Sw	DRH vs. Sw
Stage 1	507,920	508,843	30,564,884	60.18	60.07
Stage 2	8,729,744	8,730,693	686,064,039	78.59	78.58
Stage 3	789,451,894	789,451,907	51,909,640,837	65.75	65.75
Stage 4	17,158,385	17,159,321	1,246,451,248	72.64	72.64
Total	815,847,943	1,020,108,996	53,872,721,008	66.03	52.81