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EURASIP Journal on Embedded Systems

Table 15 Software speedup in multiblock data transfer phase

From: A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

  

TTPP

Card used

Process

VHDL achieved

Windows 7

Windows XP

SDHC

Multiblock read (5000 blocks)

60 μs

2.01 s

2.70 s

 

Multiblock write (5000 blocks)

100 μs

10.26 s

11.10 s

SD

Multiblock read (5000 blocks)

57 μs

1.98 s

2.46 s

 

Multiblock write (5000 blocks)

93 μs

9.89 s

10.71 s

MicroSD

Multiblock read (5000 blocks)

48 μs

1.53 s

1.99 s

 

Multiblock write (5000 blocks)

75 μs

9.12 s

10.02 s

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