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EURASIP Journal on Embedded Systems

Table 11 Clock cycles achieved for SDHC

From: A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Process

CCTPP

Initialization

336

Single block read

4176

Single block write

4184

Multiblock (5000) read

20600056

Multiblock (5000) write

20640056

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