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Table 5 Simulation results for different nodes

From: A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system

Nodes Configuration Speed-up
50 C1
50 C10 2.3 ×
80 C1
80 C10 3.26 ×
100 C1
100 C10 4.67 ×