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EURASIP Journal on Embedded Systems
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Table 2 Hardware resources and maximum frequency of the with flip-flop-based architecture for the DCT and quantizer blocks in a FPGA implementation on XilinxVirtex5
From:
FPGA implementation of JPEG encoder architectures for wireless networks
FF
LUT
F_max (MHz)
Logic
RAM
DCT_and_Quant (RAM)
4384
1870
18
79,273
DCT_8
2243
783
79,273
Intermediate_Buffer
21
9
911,328
Quantizer
313
366
18
171,851
Rounding
25
-
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