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Table 1 Hardware resources and maximum frequency of the blocks of the JPEG encoder for a FPGA implementation on a XilinxVirtex5

From: FPGA implementation of JPEG encoder architectures for wireless networks

  FF LUT F_max (MHz)
Logic RAM
Acquisition_Interface 33 8 28 527,259
Memory_Controller 216 191 16 235,383
 Memory_Read 117 57 16 235,383
 Memory_Write 99 134   422,995
JPEG_Compressor 3716 2846 1638 87,129
 Bridge_Buffers 100 241 36 396,362
 Init_JPEG 433 82 451 207,108
  Add_SOI_Marker 2 2   587,613
  Add_APP0_Marker 33 30 16 277,024
  Add_DQT_Marker 106 108 18 301,223
  Add_DHT_Marker 144 162 32 207,108
  Add_DRI_Marker 23 24   540,482
  Add_SOF_Marker 93 105 16 283,736
 Scan_Manager 735 51 834 87,129
  Init_Scan 74 100 8 87,129
  Code_A_Scan 373 404 19 147,007
  Get_A_MCU 202 225 16 241,196
  Add_SOS_Marker 82 102 94 263,630
  Add_EOI_Marker 4 4   587,613
 Get_A_DU 42 41   344,970
 DCT_and_Quant (RAM) 1757 1586 178 171,851
  DCT_8 746 536 80 258,625
  Intermediate_Buffer 21 9   911,328
  Quantizer 313 366 18 171,851
  Rounding 25    -
 Huffman_Coding 529 615 129 146,542
  DC_Coding 198 182 78 154,223
  AC_Coding 247 348 51 146,542
  RST_Marker_Manager 83 62   430,246
 BS Output_Stage 120 230 10 179,404
 SR Output_Stage 166 191 10 199,936
 FR Output_Stage 107 142 10 176,466