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Table 3 Many-object microarchitecture sequence

From: A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

 

Address

Object index

Address

Object index

Multiplexer

Cycle

0A

1A

2A

3A

0A

1A

2A

3A

0B

1B

2B

3B

0B

1B

2B

3B

0

1

2

3

1

0

0

0

0

0

1

2

3 §

1

0

0

0

4 §

1

2

3

1

2

3

0

2

0

0

0

0

0

1

2

3 §

1

1

0

0

4

5 §

2

3

2

3

0

1

3

0

0

0

0

0

1

2

3 §

1

1

1

0

4

5

6 §

3

3

0

1

2

4

0

0

0

0

0

1

2

3 §

1

1

1

1

4

5

6

7 §

0

1

2

3

5

0

0

0

0

0

1

2

3 §

2

1

1

1

8 §

5

6

7

1

2

3

0

6

0

0

0

0

0

1

2

3 §

2

2

1

1

8

9 §

6

7

2

3

0

1

7

0

0

0

0

0

1

2

3 §

2

2

2

1

8

9

§

7

3

0

1

2

8

0

0

0

0

0

1

2

3 §

2

2

2

2

8

9

§

0

1

2

3

9

0

0

0

0

0

1

2

3 §

3

2

2

2

§

9

1

2

3

0

10

1

1

1

1

4

5

6

7 §

2

1

1

1

8 §

5

6

7

1

2

3

0

11

1

1

1

1

4

5

6

7 §

2

2

1

1

8

9 §

6

7

2

3

0

1

12

1

1

1

1

4

5

6

7 §

2

2

2

1

8

9

§

7

3

0

1

2

13

1

1

1

1

4

5

6

7 §

2

2

2

2

8

9

§

0

1

2

3

14

1

1

1

1

4

5

6

7 §

3

2

2

2

§

9

1

2

3

0

15

2

2

2

2

8

§

3

2

2

2

§

9

1

2

3

0

  1. An exemplar of the sequencing of the dataflow through the many-object microarchitecture with extensibility factor m=4 and object count n=10. On each clock cycle, the microarchitecture requests the specified memory addresses from the memory groups and ports indicated. These memory addresses result in the outputting of the specified object indices. The symbols , , and § indicate the indices used in each comparison performed within the microarchtecture’s compare operation, which are chosen using the multiplexer selectors specified