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Table 5 Summary of synthesis results of original and optimized DCTs

From: A novel method for the approximation of multiplierless constant matrix vector multiplication

Objective

Optimization of the number of operations

DCTs

oper

step

ASIC

FPGA

   

A

D

P

LUTs

slices

D

P

Original

56

8

16.8

5.7

31.0

626

179

14.5

2201

Optimized

54

6

16.0

5.4

27.6

595

170

14.1

2149

ε 1=ε =4

         

Optimized

48

6

13.8

4.7

21.1

525

151

13.3

2107

ε 1=ε =8

         

Optimized

46

6

13.1

4.7

19.5

504

144

13.1

1988

ε 1=ε =16

         

Objective

Optimization under a delay constraint

DCTs

oper

step

ASIC

FPGA

   

A

D

P

LUTs

slices

D

P

Original

58

5

17.7

5.2

31.9

701

201

13.4

2079

Optimized

54

5

16.4

5.1

28.8

612

177

13.3

2058

ε 1=ε =4

         

Optimized

48

5

14.1

4.7

22.9

542

156

12.8

2088

ε 1=ε =8

         

Optimized

46

5

13.1

4.5

19.5

508

145

12.2

1874

ε 1=ε =16