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EURASIP Journal on Embedded Systems
Figure 6 | EURASIP Journal on Embedded Systems

Figure 6

From: Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures

Figure 6

Statistics collected from software bypassing and reduced connectivity for each architecture. In this figure, we present (a) the number of clock cycles normalized to the worst case of no bypassing and top-down scheduler, (b) the number of register reads and writes normalized to the case with no bypassing and top-down scheduler, (c) reduction in instruction width normalized to the case without connectivity reduction with top-down scheduler, (d) the number of connections left after connectivity reduction normalized to the case without connectivity reduction with top-down scheduler.

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