Table 5 Number of clock cycles for 2D-DCT including data transfer times between the embedded engine and the host
From: Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine
N × N-point DCT | Cycles per DCT | Latency @ 100 MHz (μ s) |
|---|---|---|
8 × 8 | 186 | 1.86 |
16 × 16 | 390 | 3.9 |
32 × 32 | 1724 | 17.24 |
64 × 64 | 6380 | 63.8 |