Table 4 Number of clock cycles for 1D-DCT including data transfer times between the embedded engine and the host
From: Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine
N-point DCT | Cyles per DCT | Latency @ 100 MHz (μ s) |
|---|---|---|
64 | 177 | 1.77 |
256 | 592 | 5.92 |
512 | 1247 | 12.47 |
1024 | 2399 | 23.99 |