Table 2 Synthesis results (with memories)
From: Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine
Up to 8K point-DFT 1D symbol 26 complex word length | |
|---|---|
Technology | IBM 130 nm CMOS technology (6 layers) |
Volt | 1.08 V |
Libraries | Gates libraries: Typical (55°c) |
|  | Fast library(125°c) used for worst case conditions |
|  | Memories library: (125°c) |
Number of Cells | 57,906 cell |
Area | 0.612 × 0.6 (0.36) mm2 |
Power | 56 mw at 100 MHz |
Max frequency | 700 MHz |