From: Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine
Algorithm | Radix-2 | Radix-4 | Radix-8 |
---|---|---|---|
Number of butterflies | 2 | 1 | 1 |
Number of stages | log2(N) | log4(N) | log8(N) |
Number of butterflies operations/stage |
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Number of clock cycles/butterflies | 1 | 1 | 2 |
Total number of clock cycles for N -point FFT |
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Normalized power | 2 | 3 | 7 |
Power efficiency | 0.5 × N × x | 0.375 × N × x | 0.43 × N × x |
As N = 2x | Â | Â | Â |