From: A DVP-Based Bridge Architecture to Randomly Access Pixels of High-Speed Image Sensors
High-performance MCU | Low-performance MCU + iBRIDGE | ||
---|---|---|---|
AT91CAP7E | AT91SAM7S512 | ATmega644 | |
Cost of programmer | Costly | Cheap | |
DIP packaging | Not available (one needs an adaptor to mount them on white boards; requires circuit design on PCB) | Available (easily mounted on white boards) | |
Firmware development (program complexity) | Relatively difficult to program; more control registers to configure; longer development time | Simpler to program; less configuration registers; shorter development time | |
Resource utilization | Low (many advanced features such as six-layer advanced high-speed bus (AHB), peripheral DMA controller, USB 2.0 full-speed device, and FPGA Interface may not be used for simple imaging application) | Medium (as some advanced features such as full-speed USB 2.0 and Real-time Timer (RTT) may not be used for simple imaging application) | High (the features are simple and may be adequate for simple imaging application) |
Power consumption | High (since large MCU is running at high clock speed at all times) | Low (since the small MCU is running at low speed at all times, however, the tiny size iBRIDGE is running at a higher speed) | |
Image sensor configuration | Complex | Simple | |
Memory capacity | Fixed (160 KB) | Fixed (64 KB) | Variable (the memory capacity can be varied depending on the application) |
Real-time random access of pixels | Complex | Simple (Row-Column addressable) | |
Power saving mode | Manual | Automated | |
I2C protocol | Needs to be configured | Already configured | |
Maximum speed (at which image sensor can be interfaced) | 80 MHz | 55 MHz | 254 MHz |
Types of image resolution supported | SubQCIF, QQVGA, QVGA | SubQCIF, QQVGA | Any resolution (SubQCIF, QQVGA, QVGA, VGA, Full HD, UHDV, etc.) |