Table 4 Synthesis results in ASIC.
From: A DVP-Based Bridge Architecture to Randomly Access Pixels of High-Speed Image Sensors
| Inputs/Outputs | 36/17 |
|---|---|
| Technology | 0.18 um CMOS |
Die dimension ( )
|
|
Core dimension ( )
|
|
| Number of cells | 1,446 |
| Number of gates | 4,735 |
| Max DCLK frequency | 254 MHz |
| Core power consumption | 13.8 mW @ 3.0 V |