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Table 3 Synthesis results on Xlinx FPGA.

From: A DVP-Based Bridge Architecture to Randomly Access Pixels of High-Speed Image Sensors

Xilinx FPGA device Area utilization Max freq. of DCLK(MHz)  
  Registers (% utilization)   Logic cells (% utilization)  
Virtex2p, XC2VP2FG256 305 (32%) 484 (51%) 248.0  
Virtex4, XC4VLX15SF363 292 (31%) 501 (53%) 200.3  
Spartan3, XC3S50TQ144 299 (31%) 492 (51%) 142.6  
Virtex E, XCV50ECS144 296 (16%) 1162 (66%) 149.5  
Virtex5, XC5VLX330 285 (37%) 368 (48%) 224.7