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Table 1 Configuration register mapping.

From: A DVP-Based Bridge Architecture to Randomly Access Pixels of High-Speed Image Sensors

CfgAdr(3 : 0) CfgData(7 : 0) CfgAdr(3 : 0) CfgData(7 : 0)
0000 Device ID 1000 Cmd2 Reg. Adr.
0001 Total Cmd. 1001 Cmd2 Reg. Data
0010 Sleep Reg. Adr. 1010 Cmd3 Reg. Adr.
0011 Sleep Reg. Data 1011 Cmd3 Reg. Data
0100 Wake Reg. Adr. 1100 Cmd4 Reg. Adr.
0101 Wake Reg. Data 1101 Cmd4 Reg. Data
0110 Cmd1 Reg. Adr. 1110 ImageWidth/4
0111 Cmd1 Reg. Data 1111 Bytes-per-pixel