Test no. | Description | Simulation period |
---|---|---|
Test 1 | TxD dominant clamp timeout | 1.1 ms |
Test 2 | Vio undervoltage timeout | 12.3 ms |
Test 3 | Loop delay TxD-CANBus_RxD |
14.0 ![]() |
Test 4 | Hoping states |
133.1 ![]() |
Test 5 | Short circuits |
210.1 ![]() |
Test 6 | Local and remote wake-up |
670.1 ![]() |
Test 7 | Power-On detection | 10.5 ms |