Skip to main content

Table 1 Performance of optimal ADC, OTA, and GDEC circuit for 3 different cost functions. denotes the system and architecture margins.

From: A Platform-Based Methodology for System-Level Mixed-Signal Design

Performance

()

()

()

DNL (LSB)

0.07

0.73

0.04

0.76

0.07

0.73

INL (LSB)

0.43

0.57

0.04

0.96

0.45

0.55

SNR (dB)

85.1

9.1

85.1

9.1

82.6

6.6

(mW)

57.1

42.9

59.6

40.4

42.6

57.4

(mW)

52.8

—

55.3

—

37.8

—

194

134

267

88.7

228

2.72

BW (KHz)

4269

1119

3768

739

2755

22.7

7.46

—

7.65

—

7.24

—

(mW)

4.2

—

4.2

—

4.8

—