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Table 3 Task latencies and Cycles/Task.

From: Virtual Prototyping and Performance Analysis of Two Memory Architectures

Task_Name

Task_0

1.21E-7

1.27E-7

247

260

Task_1

7.713E-7

7.99E-7

1579

1636

Task_2

7.235E-7

7.299E-7

1481

1494

Task_3

6.538E-7

6.605E-7

1338

1352

Task_4

8.538E-7

1.027E-6

1748

2103

Task_5

7.358E-7

7.415E-7

1506

1518

Task_6

7.453E-7

7.52E-7

1526

1540

Task_7

8.538E-7

1.0222E-6

1748

2093

Task_8

7.362E-7

7.43E-7

1507

1521

Task_9

6.783E-7

7.051E-7

1389

1444

Task_10

8.538E-7

1.0241E-6

1748

2097

Task_11

6.858E-7

7.09E-7

1404

1452

Task_12

7.1629E-7

7.216E-7

1466

1478

Task_13

8.537E-7

1.0179E-6

1748

2084

Task_14

7.298E-7

7.365E-7

1494

1508

Task_15

7.133E-7

7.196E-7

1460

1473

Task_16

8.537E-7

1.0251E-6

1748

2099

Task_17

7.11299E-7

7.169E-7

1456

1468

Task_18

6.862E-7

6.92E-7

1405

1417

Task_19

1.5795E-6

1.9301E-6

3234

3952

Task_20

7.4229E-7

7.482E-7

1520

1532

Task_21

2.6452E-6

3.3117E-6

5417

6782

Task_22

7.4649E-7

7.769E-7

1528

1591

Task_23

2.6454E-6

3.3002E-6

5417

6758

Task_24

7.4529E-7

7.52E-7

1526

1540

Task_25

2.6451E-6

3.3039E-6

5417

6766

Task_26

7.523E-7

7.58E-7

1540

1552

Task_27

2.645E-6

3.3078E-6

5416

6774

Task_28

7.458E-7

7.524E-7

1527

1540

Task_29

2.6453E-6

3.3313E-6

5417

6822

Task_30

7.9129E-7

7.976E-7

1620

1633

Task_31

2.6453E-6

3.2723E-6

5417

6701

Task_32

7.558E-7

7.6189E-7

1547

1560