Table 1 Device utilization summary after synthesis.
From: Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures
Used logic utilization | Icam_simple | Icam_complex | Robotic_vision |
|---|---|---|---|
Number of slices registers |
|
|
|
Number of slice LUTs | 3% | 6% | 9% |
Number of fully used Bit Slices | 5% | 5% | 6% |
Number of bonded IOBs | 24% | 64% | 100% |
Number of BUFG/BUFGCTRLs | 3% | 3% | 3% |
Scheduler frequency | 23,94 Mhz | 19,54 MHz | 17,44 MHz |
1%
1%
1%