EURASIP Journal on Embedded Systems

Table 3 Direct-mapped cache, average memory access time.

From: Time-Predictable Computer Architecture

Cache size	Block size	SRAM	SDRAM	DDR
1 KB	8 B	0.18	0.25	0.19
1 KB	16 B	0.22	0.22	0.16
1 KB	32 B	0.31	0.24	0.15
2 KB	8 B	0.11	0.15	0.12
2 KB	16 B	0.14	0.14	0.10
2 KB	32 B	0.22	0.17	0.11

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