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Table 2 An example of analyzable accesses to three heap-allocated objects with a four-word LRU cache. The cache content after the execution of a statement is depicted in the right section of the table.

From: Time-Predictable Computer Architecture

  

Cache state

Instruction

Memory

Youngest

Oldest

a.v = 123;

store a.v

a.v

—

—

—

b.v = 456;

store b.v

b.v

a.v

—

—

c.v = b.v;

load b.v

b.v

a.v

—

—

 

store c.v

c.v

b.v

a.v

—

d.v = b.v;

load b.v

b.v

c.v

a.v

—

 

store d.v

d.v

b.v

c.v

a.v

b.v = a.v;

load a.v

a.v

d.v

b.v

c.v

 

store b.v

b.v

a.v

d.v

c.v