Table 1 Architectural issues for WCET analysis of standard processors and proposed architectural solutions.
| Â | Standard processor WCET issues | Time-predictable processor |
|---|---|---|
Pipeline | Dependencies and shared state | Simple pipeline |
Instruction fetch | Unbounded timing effects | Avoid prefetch queue, use double buffer |
Caches | Replacement policy, abstract cache state destruction by unknown addresses | Method cache, stack cache, and a highly associative, small heap cache |
Branch prediction | Long history in dynamic predictors | Static branch prediction |
Superscalar architectures | Timing anomalies | Avoid, instead use CMP and/or VLIW |
Chip-multithreading | Interthread interference (cache, pipeline) | Avoid, instead use CMP |
Chip-multiprocessors | Intercore interference via shared memory, cache | TDMA scheduled memory access |