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Table 3 State-of-the-art LDPC decoder implementations.

From: Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes

  

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Technology

65 nm CMOS

0.16  CMOS 5-LM

0.13  TSMC CMOS

0.18  1.8 V TSMC CMOS

0.13  CMOS

Algorithm

layered

flooding

layered

TDMP

flooding/layered

CPU arch.

serial

parallel

serial

parallel

serial

Nb. of CPUs

81

1536

81

64

96

Msg. width (c2v + SO)

5 + 7

4 + 4

5 + 6

4 + 5

6

Clock fr (MHz)

240

64

500

125

333

Rates

, , ,

1/2, 2/3, 3/4, 5/6

Codeword length, N

648, 1296, 1944

1024

648, 1296, 1944

2048

Codeword size, B

27, 54, 81

1

27, 54, 81

64

Nb. of blocks,

79–88

4,33

79–88

96

76–88

Speed

Iterations

12

64

5

10

16

 

(Mbps)

262–401

1,024

541–1,618

640

177–999

Area

Kgates ()

100.7 (0.207)

1750 (52.5)

99.9 (1.85)

220 (14.3)

489.9 (2.964)

 

RAM bits

56,376

55,344

51,680

NA

Power consumption (W)

0.162

0.69

0.238

0.787

NA

(cycle/bit/iter)

1.103–1.306

0.231

1.361–1.521

0.417

1.01–1.31

(pjoule/bit/iter)

33.7–51.5

10.5

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