Table 2 IEEE 802.11n LDPC decoder complexity analysis.
From: Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes
EOP | ROP | UOP | ||
|---|---|---|---|---|
Arch. V-A | logic (Kgates) | 71.29 | 71.62 | 74.65 |
RAM bits | 61,722 | 61,722 | 61,722 | |
ROM bits | 23,159 | 23,159 | 40,788 | |
Arch. V-B | logic (Kgates) | 75.45 | 75.75 | 77.99 |
RAM bits | 53,622 | 54,837 | 57,024 | |
| 29.2% | 29.2% | 33.3% | |
| 1.1% | 4.6% | 9.1% | |
ROM bits | 36,582 | 36,582 | 51,849 | |
Arch. V-C | logic (Kgates) | 71.83 | 72.14 | 74.60 |
RAM bits | 53,217 | 53,217 | 53,784 | |
| 29.2% | 29.2% | 33.3% | |
ROM bits | 34,508 | 34,508 | 43,553 |
