SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications

EURASIP Journal on Embedded Systems

Table 6 SmartCell power consumption and energy efficiency of different benchmarks at 100 MHz.

	SmartCell		FPGA		ASIC
	Power	Throughput	Power	Throughput	Power	Throughput
	(mW)		(mW)		(mW)
FIR	152	100 MS/s	725	100 MS/s	31	100 MS/s
IIR	189	100 MS/s	896	100 MS/s	45	100 MS/s
MMM	143	763 Metrics/s	445	763 Metrics/s	36	763 Metrics/s
2D-DCT	165	2.8 MBlocks/s	795	2.8 MBlocks/s	60	2.8 Mblocks/s
ME	145	3.5 MBlocks/s	573	3.5 MBlocks/s	27	3.5 Mblocks/s
FFT	174	107 MS/s	475	100 MS/s	32	100 MS/s
PoE	150	100 MS/s	628	100 MS/s	55	100 MS/s
RC5	140	50 MBlocks/s	553	50 MBlocks/s	9	50 MBlocks/s