An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator

EURASIP Journal on Embedded Systems

Table 2 Period, area, time, and throughput comparisons.

	Xilinx XC2VP70 Slices	LUTs	Clock rate MHz	Area Time slices sec per 32 bit number
MT19937

Single port	87	—	319
624 port	1253	—	190
Software*[12]	—	—	2800	—
MT19937 [6]	420	—	76
MT19937 [7]
SMT^‡	149	—	128.02	1.16
PMT52^‡	2.850	—	71.63	0.76
FMT52^‡	11.463	—	157.60	1.45
^‡	2.914	—	62.24	0.9
^‡	5.925	—	74.16	0.77
LUT [8]
4-tap,	—	33	309	0.06^†
4-tap,	—	65	310	^†
4-tap,	—	97	298	^†
4-tap,	—	127	287	^†
4-tap,	—	257	246	^†
4-tap,	—	1249	168	^†
3-tap,	—	33	302	^†
3-tap,	—	65	319	^†
3-tap,	—	97	308	^†
3-tap,	—	127	287	^†
3-tap,	—	257	243	^†
3-tap,	—	1249	173	^†

*Software implementation was on a Pentium 4 (2.8 GHz) single core processor. ^† Each slice consists of 2 LUTs, therefore the area time rating of these desings equals LUTs/2 * Time. ^‡ This design has been implemented on an Altera Stratix. Each Xilinx slice is equivalent to two Altera logic elements.