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EURASIP Journal on Embedded Systems

Table 3 Results of the implemented architecture on a Xilinx Spartan-3 FPGA.

From: Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels

image size,

Arrowing

 

Slice flip flops

423 out of 26,624 (1%)

Occupied slices

2,658 out of 13,312 (19%)

Labelling

 

Slice flip flops

39 out of 26,624 (1%)

Occupied slices

37 out of 13,312 (1%)

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