EURASIP Journal on Embedded Systems

Table 1 Comparison of the number of clock cycles required for reading all five required values and the memory requirements for the three different methods.

From: Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels

	Sequential	Parallel	Graph-based
Clock cycles	5	1	1
Memory Req.	1x image size	5x image size	1x image size

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