EURASIP Journal on Embedded Systems

Table 6 Comparison of different FP adder architectures (5 pipeline stages).

From: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

Adder type	Slices	FFs	LUTs	Max. freq. (MHz)
LEON IP	486	269	905	71.5
LOP	570 (+17%)	294	1052	102 (+42.7%)
2-path	1026(+111%)	128	1988	200 (+180%)

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