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EURASIP Journal on Embedded Systems

Table 5 Power consumption of the neural network-based FPGA face detector by the different FPUs (unit: Mw).

From: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

Bitwidth

CLBs

RAM (Width)

Multiplier (Block)

I/O

FPU32

2

17 ( 36)

9 ( 5)

67

306

FPU24

2

17 ( 36)

7 ( 4)

49

286 (–6.5%)

FPU20

2

17 ( 36)

4 ( 2)

45

279 (–8.8%)

FPU16

2

8 ( 18)

4 ( 2)

36

261 (–14.7%)

FPU12

1

8 ( 18)

4 ( 2)

29

253 (–17.3%)

  1. Total power= sub sum + 211 mW(basic power consumption of the FPGA)
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