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Table 2 Timing results of the neural network-based FPGA face detector by different FPUs.

From: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

Bit-width

Max. Clock (MHz)

1/f(ns)

Time/1 frame (ms)

Frame rate

8.5

117

50

20

FPU32

48

21.7

8.7

114.4

FPU24

58 (+21%)

17.4

7.4

135.9

FPU20

77 (60%)

13

5.5

182.1

FPU16

80 (67%)

12.5

5.3

189.8

FPU12

85 (77%)

11.7

5

201.8

  1. General PCs use the 64-bit FPU, operating time = [(1 / Max. Clock) × 423,163 (total cycle)], frame Rate = 1000/Operating time.