Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

EURASIP Journal on Embedded Systems

Table 10 Detection rate of reduced-precision FPUs (VDHL).

Threshold	0.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8	0.9	1	Avg. detection rate error
FPU64 (PC)	35	39.09	45.91	53.64	62.73	70	72.27	77.27	78.18	77.27
FPU32 NN	35	39.09	45.91	53.64	62.73	70	72.27	76.82	78.18	77.27	0
FPU24 NN	35	39.09	45.91	53.64	62.73	70	72.27	76.82	78.18	77.27	0
FPU20 NN	35	39.09	46.36	53.64	63.18	70	73.64	76.82	77.73	76.82	0.36
FPU18 NN	35	41.36	47.73	56.82	65.46	69.55	74.55	77.73	77.27	74.09	1.73
FPU16 NN	35.91	44.55	53.18	66.36	70.46	76.36	78.18	74.55	72.73	72.73	5.91
	0.91	5.45	7.27	12.73	7.73	6.36	5.91	2.73	5.46	4.55	5.91