| [ 33 ] | [ 34 ] | [ 35 ] | [ 36 ] | Proposed architecture |
---|---|---|---|---|---|
Type | ASIC | ASIC | ASIC | ASIC | FPGA + DSP |
Algorithm | FS | FS | FS | FS | ACQPPS |
Search range | [−16, +15] | [−32, +31] | [−16, +15] | [−16, +15] | Flexible |
Gate count | 103 K | 154 K | 67 K | 108 K | 35 K |
 |  |  |
| Â | Â |
Support block sizes | All | All |
| All | All |
 |  |  |
| Â | Â |
Freq. [MHz] | 66.67 | 100 | 60 | 100 | 75 |
Max fps of CIF | 102 | 60 | 30 | 56 | 120 |
Min Freq. [MHz]for CIF 30 fps | 19.56 | 50 | 60 | 54 | 18.75 |