Skip to main content
  • Research Article
  • Open access
  • Published:

The Chameleon Architecture for Streaming DSP Applications

Abstract

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33]

References

  1. ETSI : Broadband Radio Access Networks (BRAN); HiperLAN type 2; Physical (PHY) layer. ETSI TS 101 475 V1.2.2 (2001-2002), 2001

  2. Ojanperä T: Wideband CDMA for Third Generation Mobile Communications, The Artech House Universal Personal Communications Series. Artech House, Norwood, Mass, USA; 1998.

    Google Scholar 

  3. Dally WJ, Kapasi UJ, Khailany B, Ahn JH, Das A: Stream processors: programmability with efficiency. ACM Queue 2004,2(1):52-62. 10.1145/984458.984486

    Article  Google Scholar 

  4. Mansour O: High level synthesis for non-manifest digital signal processing applications, Ph.D. thesis. University of Twente, Twente, The Netherlands; 2006.

    Google Scholar 

  5. Tessier R, Burleson W: Reconfigurable computing for digital signal processing: a survey. The Journal of VLSI Signal Processing 2001,28(1-2):7-27. 10.1023/A:1008155020711

    Article  MATH  Google Scholar 

  6. Latva-aho M, Juntti M, Oppermann I: Reconfigurable adaptive RAKE receiver for wideband CDMA systems. Proceedings of the 48th IEEE Vehicular Technology Conference (VTC '98), May 1998, Ottawa, Ontario, Canada 3: 1740-1744.

    Google Scholar 

  7. Lala PK, Walker A: An on-line reconfigurable FPGA architecture. Proceedings of the 15th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '00), October 2000, Yamanashi, Japan 275-280.

    Chapter  Google Scholar 

  8. Bolsens I: Challenges and opportunities for FPGA platforms. Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02), September 2002, Montpellier, France 391-392.

    Google Scholar 

  9. Held I, VanderWiele B: Avispa-CH - embedded communications signal processor for multi-standard digital television. GSPx TV to Mobile, March 2006

  10. Baumgarte V, May F, Nuckel A, Vorbach M, Weinhardt M: PACT XPP—a self-reconfigurable data processing architecture. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '01), June 2001, Las Vegas, Nev, USA 64-70.

    Google Scholar 

  11. Abnous A: Low-power domain-specific processors for digital signal processing, Ph.D dissertation.

  12. Heysters PM, Smit GJM: Mapping of DSP algorithms on the MONTIUM architecture. Proceedings of Reconfigurable Architectures Workshop (RAW '03), April 2003, Nice, France

    Google Scholar 

  13. Heysters PM: Coarse-grained reconfigurable processors - flexibility meets efficiency, Ph.D. thesis. University of Twente, Twente, The Netherlands; 2004.

    Google Scholar 

  14. Smit GJM, Schuler E, Becker JE, Quevremont J, Brugger W: Overview of the 4S project. Proceedings of the International Symposium on System-on-Chip (SoC '05), November 2005, Tampere, Finland 70-73.

    Google Scholar 

  15. Burns G, Gruijters P, Huisken J, van Wel A: Reconfigurable accelerator enabling efficient SDR for low-cost consumer devices. SDR Technical Forum, November 2003, Orlando, Fla, USA

    Google Scholar 

  16. Virtex II Pro and Virtex II pro X FPGA UserGuide 2005.

  17. Yarlagadda K: ARM refocuses DSP effort. In Microprocessor report, Micro-design resources. Consorci de Biblioteques Universitàries de Catalunya, Barcelona, Spain; 1999.

    Google Scholar 

  18. Heysters PM, Smit LT, Smit GJM, Havinga PJM: Max-log-MAP mapping on an FPFA. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '02), June 2002, Las Vegas, Nev, USA 90-96.

    Google Scholar 

  19. Zhang H, Wan M, Gearge V, Rabaey J: Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs. Proceedings of the IEEE Computer Society Workshop on VLSI (WVLSI '99), April 1999, Orlando, Fla, USA 2.

    Google Scholar 

  20. Goossens K, van Meerbergen J, Peeters A, Wielage R: Networks on silicon: combining best-effort and guaranteed services. Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '02), March 2002, Paris, France 423-425.

    Google Scholar 

  21. Kavaldjiev N, Smit GJM, Jansen PG, Wolkotte PT: A virtual channel network-on-chip for GT and BE traffic. Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI '06), March 2006, Karlsruhe, Germany 211-216.

    Chapter  Google Scholar 

  22. Wolkotte PT, Smit GJM, Rauwerda GK, Smit LT: An energy-efficient reconfigurable circuit-switched network-on-chip. Proceedings of the 12th Reconfigurable Architectures Workshop (RAW '05), April 2005, Denver, Colo, USA

    Google Scholar 

  23. Wolkotte PT, Smit GJM, Becker JE: Energy-efficient NOC for best-effort communication. Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL '05), August 2005, Tampere, Finland 197-202.

    Google Scholar 

  24. Rexford J, Shin KG: Support for multiple classes of traffic in multicomputer routers. In Proceedings of the 1st International Workshop on Parallel Computer Routing and Communication (PCRCW '94), May 1994, Seattle, Wash, USA. Springer; 116-130.

    Chapter  Google Scholar 

  25. Dielissen J, Rădulescu A, Goossens K, Rijpkema E: Concepts and implementation of the phillips network-on-chip. IP-Based SOC Design, November 2003, Grenoble, France

    Google Scholar 

  26. Wiklund D, Liu D: Socbus: switched network on chip for hard real time embedded systems. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS '03), April 2003, Nice, France 78a.

    Google Scholar 

  27. van de Burgwal MD, Smit GJM, Rauwerda GK, Heysters PM: Hydra: an energy-efficient and reconfigurable network interface. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06), June 2006, Las Vegas, Nev, USA 171-177.

    Google Scholar 

  28. Guo Y: Mapping applications to a coarse-grained reconfigurable architecture, Ph.D. thesis. University of Twente, Twente, The Netherlands; 2006.

    Google Scholar 

  29. Koester M, Porrmann M, Kalte H: Task placement for heterogeneous reconfigurable architectures. Proceedings of IEEE International Conference on Field Programmable Technology (FPT '05), December 2005, Singagore 43-50.

    Google Scholar 

  30. Smith King LA, Leeser M, Quinn H: Dynamo: a runtime partitioning system. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04), June 2004, Las Vegas, Nev, USA 145-151.

    Google Scholar 

  31. Fu W, Compton K: An execution environment for reconfigurable computing. Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '05), April 2005, Napa, Calif, USA 149-158.

    Google Scholar 

  32. Smit LT, Hurink JL, Smit GJM: Run-time mapping of applications to a heterogeneous SoC. Proceedings of the International Symposium on System-on-Chip (SoC '05), November 2005, Tampere, Finland 78-81.

    Google Scholar 

  33. Aggarwal G, Motwani R, Zhu A: The load rebalancing problem. Proceedings of the 15th Annual ACM Symposium on Parallelism in Algorithms and Architectures (SPAA '03), June 2003, San Diego, Calif, USA 258-265.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Gerard JM Smit.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Smit, G.J., Kokkeler, A.B., Wolkotte, P.T. et al. The Chameleon Architecture for Streaming DSP Applications. J Embedded Systems 2007, 078082 (2007). https://doi.org/10.1155/2007/78082

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/78082

Keywords