Open Access

pn: A Tool for Improved Derivation of Process Networks

EURASIP Journal on Embedded Systems20072007:075947

DOI: 10.1155/2007/75947

Received: 30 June 2006

Accepted: 10 January 2007

Published: 11 April 2007

Abstract

Current emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor architectures. System designers experience significant difficulties in programming these platforms. The applications are typically specified as sequential programs that do not reveal the available parallelism in an application, thereby hindering the efficient mapping of an application onto a parallel multiprocessor platform. In this paper, we present our compiler techniques for facilitating the migration from a sequential application specification to a parallel application specification using the process network model of computation. Our work is inspired by a previous research project called Compaan. With our techniques we address optimization issues such as the generation of process networks with simplified topology and communication without sacrificing the process networks' performance. Moreover, we describe a technique for compile-time memory requirement estimation which we consider as an important contribution of this paper. We demonstrate the usefulness of our techniques on several examples.

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Authors’ Affiliations

(1)
Leiden Institute of Advanced Computer Science (LIACS), Leiden University

References

  1. Darte A, Schreiber R, Villard G: Lattice-based memory allocation. IEEE Transactions on Computers 2005, 54: 1242-1257. 10.1109/TC.2005.167View ArticleGoogle Scholar
  2. Lee EA, Sangiovanni-Vincentelli A: A framework for comparing models of computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1998,17(12):1217-1229. 10.1109/43.736561View ArticleGoogle Scholar
  3. Davis J, Galicia R, Goel M, et al.: PtolemyII: heterogeneous concurrent modeling and design in java. In Tech. Rep. UCB/ERL M99/40. University of California, Berkeley, Calif, USA; 1999.Google Scholar
  4. Kahn G: The semantics of a simple language for parallel programming. In Proceedings of the IFIP Congress, August 1974, Stockholm, Sweden. North-Holland; 471-475.Google Scholar
  5. de Kock EA, Essink G, Smits WJM, et al.: YAPI: application modeling for signal processing systems. Proceedings of the 37th Design Automation Conference (DAC '00), June 2000, Los Angeles, Calif, USA 402-405.Google Scholar
  6. de Kock EA: Multiprocessor mapping of process networks: a JPEG decoding case study. Proceedings of the 15th International Symposium on System Synthesis (ISSS '02), October 2002, Kyoto, Japan 68-73.Google Scholar
  7. Dwivedi BK, Kumar A, Balakrishnan M: Automatic synthesis of system on chip multiprocessor architectures for process networks. In Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, (CODES+ISSS '04), September 2004, Stockholm, Sweden. IEEE Computer Society; 60-65.Google Scholar
  8. Goossens K, Dielissen J, van Meerbergen J, et al.: Guaranteeing the quality of services in networks on chip. In Networks on Chip. Kluwer Academic Publishers, Hingham, Mass, USA; 2003:61-82.View ArticleGoogle Scholar
  9. Lieverse P, Stefanov T, van der Wolf P, Deprettere E: System level design with SPADE: an M-JPEG case study. Proceedings of the International Conference on Computer-Aided Design (ICCAD '01), November 2001, San Jose, Calif, USA 31-38.Google Scholar
  10. Nieuwland A, Kang J, Gangwal OP, et al.: C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. Kluwer Academic Publishers, Norwell, Mass, USA; 2002.Google Scholar
  11. Nikolov H, Stefanov T, Deprettere E: Multi-processor system design with ESPAM. Proceedings of the 4th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), October 2006, Seoul, Korea 211-216.View ArticleGoogle Scholar
  12. Pimentel AD, Erbas C, Polstra S: A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers 2006,55(2):99-112. 10.1109/TC.2006.16View ArticleGoogle Scholar
  13. Stefanov T, Zissulescu C, Turjan A, Kienhuis B, Deprettere E: System design using Kahn process networks: the Compaan/Laura approach. Proceedings of Conference Design, Automation and Test in Europe (DATE '04), February 2004, Paris, France 1: 340-345.View ArticleGoogle Scholar
  14. van der Wolf P, Lieverse P, Goel M, La Hei D, Vissers K: MPEG-2 decoder case study as a driver for a system level design methodology. Proceedings of the 7th International Workshop on Hardware/Software Codesign (CODES '99), May 1999, Rome, Italy 33-37.Google Scholar
  15. Kienhuis B, Rijpkema E, Deprettere E: Compaan: deriving process networks from matlab for embedded signal processing architectures. In Proceedings of the 8th International Workshop Hardware/Software Codesign (CODES '00), May 2000, San Diego, Calif, USA. ACM Press; 13-17.Google Scholar
  16. Rijpkema E, Deprettere EF, Kienhuis B: Deriving process networks from nested loop algorithms. Parallel Processing Letters 2000,10(2):165-176. 10.1142/S0129626400000172View ArticleGoogle Scholar
  17. Turjan A, Kienhuis B, Deprettere E: Translating affine nested-loop programs to process networks. Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '04), September 2004, Washington, DC, USA 220-229.Google Scholar
  18. Darte A, Schreiber R, Villard G: Lattice-based memory allocation. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '03), October-November 2003, San Jose, Calif, USA. ACM Press; 298-308.View ArticleGoogle Scholar
  19. Beyls K, D'Hollander EH: Generating cache hints for improved program efficiency. Journal of Systems Architecture 2005,51(4):223-250. 10.1016/j.sysarc.2004.09.004View ArticleGoogle Scholar
  20. Vander Aa T, Jayapala M, Barat F, Corporaal H, Catthoor F, Deconinck G: A high-level memory energy estimator based on reuse distance. Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES '05), March 2005, San Jose, Calif, USA Google Scholar
  21. Vanbroekhoven P, Janssens G, Bruynooghe M, Corporaal H, Catthoor F: Advanced copy propagation for arrays. In Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES '03), June 2003, San Diego, Calif, USA. Edited by: Kremer U. ACM Press; 24-33.Google Scholar
  22. Feautrier P: Automatic parallelization in the polytope model. In The Data Parallel Programming Model, Lecture Notes in Computer Science. Volume 1132. Springer, London, UK; 1996:79-103.View ArticleGoogle Scholar
  23. Feautrier P: Parametric integer programming. Operationnelle/Operations Research 1988,22(3):243-268.MATHMathSciNetGoogle Scholar
  24. Verdoolaege S, Seghir R, Beyls K, Loechner V, Bruynooghe M: Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations. Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '04), September 2004, Washington, DC, USA 248-258.Google Scholar
  25. Clauss P, Fernández FJ, Gabervetsky D, Verdoolaege S: Symbolic polynomial maximization over convex sets and its application to memory requirement estimation. In ICPS Research Reports 06–04. Université Louis Pasteur, Strasbourg, France; 2006. http://icps.u-strasbg.fr/upload/icps-2006-173.pdf Google Scholar
  26. Feautrier P: Dataflow analysis of array and scalar references. International Journal of Parallel Programming 1991,20(1):23-53. 10.1007/BF01407931MATHView ArticleGoogle Scholar
  27. Bastoul C: Code generation in the polyhedral model is easier than you think. In Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT '04), September 2004, Antibes Juan-les-Pins, France. IEEE Computer Society; 7-16.Google Scholar
  28. Verdoolaege S, Bruynooghe M, Janssens G, Catthoor F: Multi-dimensional incremental loop fusion for data locality. In Proceedings of the 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '03), June 2003, The Hague, The Netherlands Edited by: Martin D. 17-27.Google Scholar
  29. Verdoolaege S, Danckaert K, Catthoor F, Bruynooghe M, Janssens G: An access regularity criterion and regularity improvement heuristics for data transfer optimization by global loop transformations. Proceedings of the 1st Workshop on Optimization for DSP and Embedded Systems (ODES '03), March 2003, San Francisco, Calif, USA Google Scholar
  30. Daubechies I, Sweldens W: Factoring wavelet transforms into lifting steps. Journal of Fourier Analysis and Applications 1998,4(3):247-269. 10.1007/BF02476026MATHMathSciNetView ArticleGoogle Scholar

Copyright

© Verdoolaege et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.